1. Field of the Invention
The present invention relates to a method of erasing information in a non-volatile semiconductor memory device. More particularly, the present invention relates to a method of erasing information in a non-volatile semiconductor memory device including a memory cell having a stacked film formed of an oxide film, a nitride film and an oxide film (abbreviated as “ONO film” hereinafter).
2. Description of the Background Art
An MONOS (Metal OxyNitride Oxide Semiconductor) type non-volatile semiconductor memory device as one type of non-volatile semiconductor memory devices includes a so-called NROM (Nitrided Read Only Memory) 120 capable of handling two-bit information in one cell 110 as shown in FIG. 17.
In an individual cell, for example as shown in FIG. 18, an ONO film 105 formed of silicon oxide films 105a, 105c and silicon nitride film 105b has a floating gate structure. Of three films constituting ONO film 105, silicon nitride film 105b serves as a floating gate.
A pair of impurity regions 103a and 103b serving as a source/drain region are formed in one region and other region of a semiconductor substrate 101 with ONO film 105 interposed therebetween. A control gate electrode 107 of a polysilicon film or of a polycide structure is formed on ONO film 105.
Information is written by injecting channel hot electrons (simply referred to as “electron” hereinafter) into two separate portions, that is, a portion positioned on the side of one impurity region 103a and a portion positioned on the side of the other impurity region 103b, of, a pair of impurity regions 103a and 103b, respectively, in silicon nitride film 105b. Two-bit information can thereby be handled in one cell.
As an operation of erasing information written by injecting electrons, an operation of erasing information written in only one bit of two bits will now be described.
FIG. 18 shows electrons 111 as information injected into the portion positioned on the one impurity region 103a side in silicon nitride film 105b. In this state, a potential of 0V is applied to control gate electrode 107 and the pair of impurity regions 103a and 103b, respectively.
Then, as shown in FIG. 19, a potential of 8V is applied to one impurity region 103a, and the other impurity region 103b is brought into a floating state. Therefore electrons 111 in silicon nitride film 105b are pulled off toward one impurity region 103a as indicated by arrow 115.
Furthermore, as shown in FIG. 21, when electrons 111 are injected into the portion positioned on the other impurity region 103b side in silicon nitride film 105b, the erasing operation is also performed in a manner similar to the erasing operation as described above.
In this case, as shown in FIG. 22, a potential of 8V is applied to the other impurity region 103b while one impurity region 103a is brought into a floating state, so that electrons 111 in silicon nitride film 105b are pulled off toward the other impurity region 103b as indicated by arrow 115.
As the operation of erasing information written by injecting electrons, the operation of erasing information written in both two bits as shown in FIG. 24 at one time will now be described.
In this case, as shown in FIG. 25, a potential of 5V is applied to one impurity region 103a and the other impurity region 103b, respectively, while a potential of −3V is applied to control gate electrode 107.
Therefore, electrons 111 located on the one impurity region 103a side in silicon nitride film 105b is pulled off toward one impurity region 103a as indicated by arrow 115, and electrons 111 located on the other impurity region 103b side are pulled off toward the other impurity region 103b as indicated by arrow 115. In this manner, the operation of erasing information is performed in NROM 120.
The aforementioned erasing operation in NROM 120, however, has the following problems. In writing information, as shown in FIGS. 18, 21 or 24, electrons 111a may be trapped accidentally in that part of silicon nitride film 105b which is positioned immediately above a region approximately at the midpoint between one impurity region 103a and the other impurity region 103b. 
These electrons 111a are not pulled off in the erasing operations respectively shown in FIGS. 19, 22 and 25 as described above and still remain in silicon nitride film 105b even after the erasing operation as shown in FIGS. 20, 23 and 26, respectively. Therefore, electrons 111a are accumulated in silicon nitride film 105b after the erasing operation, resulting in variations of threshold voltages in cell 110. It is noted that electrons 111a remaining in silicon nitride film 105b are referred to as “MPE” (Miss Placed Electrons), in particular.